A 2.2GHz Sub-Sampling PLL with 0.16psrms Jitter and -125dBc/Hz In-band Phase Noise at 700μW Loop-Components Power

A divider-less PLL exploits a phase detector that directly samples the VCO with a reference clock. No VCO sampling buffer is used while dummy samplers keep the VCO spur <-56dBc. A modified inverter with low short-circuit current acts as a power efficient reference clock buffer. The 2.2GHz PLL in 0.18μm CMOS achieves -125dBc/Hz in-band phase noise with only 700μW loop-components power. Introduction Clock multiplication PLLs with very low jitter have recently been proposed based on sub-sampling [1,2] and injection locking [3,4]. In a PLL, the VCO dominates the out-of-band phase noise while the loop-components dominate the in-band phase noise. The sub-sampling (SS) PLL [1,2] can achieve very low in-band phase noise because: 1) divider noise is eliminated; 2) the phase detector (PD) and charge pump (CP) noise is not multiplied by N. This paper describes a new SSPLL design aiming to drastically reduce the loop-components power while maintaining its superior in-band phase noise performance. Proposed Low Power SSPLL Fig. 1(a) shows the low power SSPLL architecture. A sub-sampling phase detector (SSPD) samples the VCO with a reference clock Ref and converts VCO phase error into sampled voltage variation. A CP converts the sampled voltage to current. A Pulser controls the CP gain and simplifies the SSPD design to a track-and-hold [1]. A frequency locked loop ensures correct frequency locking and is disabled after locking to save power. In a SSPLL the PD and CP noise contributions are low and thus their power can be scaled down progressively. The VCO and Ref buffers for the SSPD then become the bottlenecks for low power. In [1], they account for 30% and 60% of the total loop-components power, respectively. In this design, we propose two techniques to alleviate these bottlenecks: 1) direct sampling of the VCO without buffer while keeping the disturbance to the VCO low; 2) power efficient Ref buffering with drastically reduced short-circuit current. Fig. 2 shows the LC VCO and SSPD schematic. Different from [1], no buffer is used between the VCO and SSPD samplers. This saves power as buffers running at fVCO are power consuming. The samplers use PMOS switches since the VCO DC level is high. A concern of this buffer-less direct VCO sampling is the disturbance to the VCO operation. When Ref turns on/off the sampling switch, the VCO is loaded/un-loaded by the sampling capacitors Csam. The VCO load and thus fVCO is changed resulting in binary frequency shift keying (BFSK), causing spurs at integer multiples of fref. In order to reduce this effect, dummy samplers are added as (a) Frequency locked loop PFD/CP with dead zone ÷ N VCO XO VCO Low Power Buffer CP